Xilinx axi gpio interrupt Now i try to detect an interrupt. semaphores or queues with their handles) are properly created before enabling interrupts I am using an AXI GPIO in the PL, configured as digital input, that is connected to an external PWM signal. You know, without scheduling tasks a multi-tasing RTOS is pretty useless As Richard pointed out when enabling interrupts and using FreeRTOS API in the ISR you’ve to ensure that all necessary resources (e. h&quot; #include &quot;xscugic. Zynq UltraScale+ MPSoC. For details, see xgpio_intr_tapp_example. (And it appears just to facilitate this demonstration that UIO was included- is that correct?) But the axi_gpio interrupt was already showing up in /proc/interrupts. c For example, lets take a simple AXI GPIO interrupt connected to the SCUGIC on the Zynq Ultrascale PSU If we generate a platform in Vitis Unified IDE using the XSA generated here, and look at the xparameters. Nearly every Embedded system will contain Interrupts in one shape or another. * Therefore, only rising edge or falling edge triggers are Hello, I have the following hardware: For the software, the interrupt part, I copied from a previous project where I had a custom IP generating the interrupt source so I thought it would be copying and pasting. h" #include "xil_printf. Here is the software: #include "xparameters. Contribute to Xilinx/embeddedsw development by creating an account on GitHub. You can see that axi_gpio_1 is created. Make sure that the IRQ is registered: cat /proc/interrupts; You Use PS HPM LPD AXI to control the AXI interface of the GPIO and timer. And many tutorials use two AXI-GPIO to demonstrate how to use the PL-to-PS interrupt, one for output and another for input interrupts. The connections are highlighted. 354761] XGpio: /amba_pl@0/gpio@80010000: registered, base is 496 The AXI GPIO driving the LEDs is at 0x80000000 so its base is 504. The GPIO core consists of registers and multiplexers for reading and writing the AXI GPIO channel Test the Interrupt. sdk. Interrupts are tested on PetaLinux 2020. Laptops; Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. ip2intc_irpt System O 0 AXI GPIO Interrupt. c (located at Add the second AXI GPIO IP: Copy the axi_gpio_0 IP by typing Ctrl+C. dtsi is different in a notable way: axi_intc_0: interrupt In my design I use a few AXI GPIO blocks, that generate control bits and receive status words from other IP cores. com/lessons. So custom Kernel module was tried but interrupt was not getting fired in driver. Device Family: Virtex UltraScale+; Kintex UltraScale+; Zynq UltraScale+ MPSoC; Virtex UltraScale; Kintex UltraScale; Zynq-7000; Virtex I created a Arty-A7-35T Vivado 2018. Set up the AXI_GPIO to generate an interrupt anytime one of the The Interrupts control gets the interrupt status from the GPIO channels and generates an interrupt to the host. I have configured the GPIO to trigger an interrupt for both rising and falling edges and a timer, so I can calculate the duty cycle of the signal. h: xgpio_intr. And here we are not using interrupt priority. Enable AXI HPM0 LPD, expand it, and set the AXI HPM0 LPD Data Width I am trying to implement an interrupt routine on my Arty board. AXI GPIO: The General Purpose Input/output Add the second AXI GPIO IP: Copy the axi_gpio_0 IP by typing Ctrl+C. I have experience with using IRQ's on AXI GPIO , DMA, . Regards, The Xilinx® LogiCORE™ IP AXI General Purpose Input/Output (GPIO) core provides a general purpose input/output interface to the AXI interface. In Vitis Unified, we have made the interrupts easier to add to your baremetal application code with the addition of the interrupt wrapper. at com. cat Hi Experts, My setup and environment is as below: Petalinux v2021. Feature Summary Interrupt conditions are AXI GPIO: The General Purpose Input/output (GPIO) core is an interface that provides easy access to the internal properties of the device. Configure axi_gpio_1 for PL Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. #define INTC_GPIO_INTERRUPT_ID XPAR_FABRIC_AXI_GPIO_0_IP2INTC_IRPT_INTR #define Below is a snippet of the register space from the AXI GPIO product guide For example, we can use the devmem utility to write to this register from the linux console: Then rerun, the cat /proc/interrupts and the interrupt count should be incremented for the gpio: If users would like to debug a Linux application in SDK, then they can follow on from here with the wiki Just a shot into blue: If there are multiple interrupt handlers (for multiple buttons) and XGpio_InterruptGetStatus() detects that the current handler was called for the wrong button, then the call of the right handler might be already pending. Then this square wave will go to my AXI GPIO, and GPIO IP can detect the rising/falling edge of my square wave to generate an interrupt. Xilinx Wiki. All functions used to Forcing an apparent interrupt by writing to the axi_gpio's interrupt status register demonstrates an increment in the interrupt count shown in /proc/interrupts. My goal is to use AXI GPIO IP to generate a correct interrupt to the PS every 10us. c file) reads the "axi_gpio_0_GPIO_I_pin" value and write it to the To implement this example and write the elements identified above, we will need to use functions contained with the Xilinx PS GPIO, PS Generic Interrupt Controller and Exception drivers. Content. AXI Interrupt Controller s_axi s_axi_aclk s_axi_aresetn intr[16:0] irq axi_interconnect AXI Interconnect S00_AXI M00_AXI M01_AXI M02_AXI M03_AXI M04_AXI M05_AXI M06_AXI M07_AXI M08_AXI M09_AXI M10_AXI M11_AXI M12_AXI M13_AXI M14_AXI M15_AXI M16_AXI M17_AXI M18_AXI M19_AXI M20_AXI AXI GPIO S_AXI GPIO gpio_io_o[0:0] s_axi_aclk Below is a snippet of the register space from the AXI GPIO product guide For example, we can use the devmem utility to write to this register from the linux console: Then rerun, the cat /proc/interrupts and the interrupt count should be incremented for the gpio: If users would like to debug a Linux application in SDK, then they can follow on from here with the wiki Forcing an apparent interrupt by writing to the axi_gpio's interrupt status register demonstrates an increment in the interrupt count shown in /proc/interrupts. I can read the value of the 4 pushbuttons in uio. Xilinx AXI GPIO interrupts are used in the Vivado design. This 32-bit soft Intellectual Property (IP) core is designed to interface with the AXI4-Lite interface. But when taking into software integration, one interrupt is working another is not working means PS GPIO interrupt is working but PL-PS GPIO interrupt is not working. This way core0 can generate a signal that is propagated to PL and then received in core1. Hello, The AXI GPIO IP (2018. the connected blocks: AXI GPIO Block AXI Interconnect Zynq PS Processor System Reset [Zedboard] AXI-GPIO interrupt not working. 1 Product Guide 6 PG099 July 15, 2021 www. The pin is set up as 'intr' In petalinux I set up an interrupt controller like this: pl_int@80000000 { compatible = "generic-uio"; interrupt-parent = <&gic>; interrupts = <0 89 1>; }; And I can see the interrupt with cat /proc/interrupt : This driver does not supply linux gpio interface. Click OK to accept the This file contains a design example using the AXI GPIO driver and hardware device : xgpio_extra. This is not my case. The GPIO subsystem is documented in the kernel documentation in Documentation/gpio/. Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. So i don't want to use the UIO / Sysfs method for handling interrupt. Click OK. 2. Seems like it would it be better to simply route a signal directly into the PL-PS interrupt at this point. In current version, you can set and get the value of the IO channel, enable and disable the interrupt, and receive the SIGIO signal if the interrupt is enabled. Gen_data is simple module (source code). Calendars. Comparing the good with the bad builds, I noticed that the axi-intc portion of pl. c: This file contains a design example using the GPIO driver in an interrupt driven mode of operation : xgpio_l. Double-click the Zynq UltraScale+ MPSoC IP block. micro-studios. My goal is to set up a simple AXI configurable interrupter in the PL of a Zynq and use it trigger a handler inside freeRTOS running on the PS. ° Writes the vector address of the active interrupt in IVR register and enables the IPR register for pending interrupts. Connect the 4 buttons to an AXI_GPIO. Linux. handlers. Well, I have a block diagram with a single AXI Interrupt Controller and *FOUR* different interrupting blocks (one AXI UART LITE and three AXI GPIO) blocks. A Simplified Model of the ZynqArchitecture Source: The Zynq Book . This core can also be used to control the behavior of the external devices. com 2 Product Specification LogiCORE IP AXI GPIO (v1. currently, individually working perfect. Faced issues with UIO in handling fast interrupt. I can connect to the particular GPIO using the struct gpio thanks @balkriskri7, the AR's are indeed a bit outdated :-). gpio_io_i (1)(3) GPIO I Channel 1 general purpose input Added a GPIO peripheral with Interrupt enabled to my XPS design and connected the interrupt signal to the xps_intc controller. I do not want to use GPIO-keys or UIO because they need a blocking read BUT I want to write a kernel module and register the axi-gpio interrupt in that by interrupt request function (request_irq()) and register a ISR for it. But I was using de Xgpio lib which is the AXI GPIO driver, different from ps GPIOs. xgpio_intr_tapp_example. Customize the AXI GPIO IP block:. AMD-Xilinx Wiki Home. The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a single interrupt output to the system processor. However, the ISR I defined is never called. Hello everyone, i'd like to use an interrupt from a pushbutton. 2, targeting a VCK190 evaluation board. Upon configuration I am successfully able to generate an interrupt from the GPIO inputs on the PS. I enabled interrupts in axi_gpio ip and fabric interrupts www. c provided by xilinx SDK code found here: C:\Xilinx\SDK\2018. The fabric design is quite simple, as you can see in the block diagram*, with an interrupt from the gpio block connected to the Zedboard buttons. I am using the following code to handle interrupts generated the IP. I'm able to drag a The Xilinx® LogiCORE™ IP AXI General Purpose Input/Output (GPIO) core provides a general purpose input/output interface to the AXI interface. Also, the vector table entries seem to match but the ISR do not It only uses channel 1 of a GPIO device and assumes that the bit 0 of the GPIO is connected to the LED on the HW board. h&quot; #include &quot;xuartps. ui. The problem is that, in the interrupt handler, I don't know how to check what event (rising An AXI GPIO interrupt can be used to test the UIO driver functionality. 2\data\embeddedsw\XilinxProcessorIPLib\drivers\gpio_v4_3\examples. I find the AXI-GPIO can enable two channels. I use the Zedboard Y9 100MHZ clock resource at PL and a super simple custom IP to counter 100times and generate a square wave. Here is my design: I used the example code that Xilinx offers and here is my code. Configure axi_gpio_0 for push buttons: Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. RegenBspSourcesHandler. * The example uses the interrupt capability of the GPIO to detect push button * events and set the output LEDs based on the input. Here peripherals used are axi_timer, can and canfd All the interrupt pins af timer, can and canfd are connected to axi_intc and the axi_intc cascaded to GIC(IRQ_F2P) Test cases: DTG should generate proper interrupts information as an example below axi_gpio {interrupt-parent = "axi_intc"; interrupt-id = <0 1>;} axi_interrupt-controller Xilinx AXI GPIO interrupts are used in the Vivado design. Contains an example on how to use the XGpio driver directly. 2. Products Processors Accelerators Graphics Adaptive SoCs, FPGAs, & SOMs Software, Tools, & Apps . AXI GPIO: The General Purpose Input/output (GPIO) core is an interface that provides the input and output access to the interfaced devices. Zynq UltraScale+ RFSoC. AMD-Xilinx Wiki Home This trigger is hidden. Linux Prebuilt Images. Frequency is 100 Mhz. Versal Adaptive SoCs. All content. It is enabled when the Enable Interrupt option is set in the Vivado® Integrated Design GPIO core provides an interface between the IPIC interface and the AXI GPIO channels. Search for “AXI GPIO” and double-click the AXI GPIO IP to add it to the design. Select the IP Configuration page. For details, see xgpio_example. Ensure that All Inputs and All Outputs are both unchecked. amd. The whole system is built in the Block Designer. Performance. AMD Website Accessibility Statement. Configure axi_gpio_0 for push buttons: Double-click axi_gpio_0 to open its configurations. The driver has only ioctl interface. txt . I study to work with FPGA (Xilinx Kintex Ultrascale). Open Source Projects. I want to use the switches on the board to generate the interrupt. EPYC; Business Systems. Starting the scheduler basically starts a FreeRTOS application. gpio_io_i (1)(3) GPIO I Channel 1 general purpose input The AXI GPIO provides a general purpose input/output interface to the AXI (Advanced eXtensible Interface) interface. h" #include ";xgpio. Shortcuts. - The interrupts are firing based on axi gpio 0 (which is connected to my pushbuttons), - My PWM block is outputting a PWM waveform that triggers the interrupt (I soldered a jumper wire from the PWM output [pin A0] to BTN0 on the board) (Xilinx Software Command line Tool) to read/write values from/to registers. * * @note * This example assumes that there is a Uart device in the HW design. I also added corresponding net / interface connection properties. Enter a <*> beside Xilinx AI Engine driver; Below is a snippet of the register space from the AXI GPIO. c: xgpio_intr_tapp_example. access$2 (RegenBspSourcesHandler. For more information, GPIO Interrupt Example Test Push Switch button to exit Successfully ran GPIO Interrupt Example Test Example Design Architecture. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface. Using the debugger in SDK confirms that the Axi INTC core is configured and working properly by reading the master enable register and interrupt pending register. Interrupts: The Interrupts control gets the interrupt status from the GPIO channels and generates an interrupt to the host. I selected the blocks directly connected to the AXI GPIO Block. c. xilinx. dtsi file looks like: / { amba_pl: amba_pl@0 { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; axi Generate an interrupt signal from core0 (via axi GPIO and connect it to zynq interrupt). AXI gpio standalone driver The Xilinx® LogiCORE™ IP AXI General Purpose Input/Output (GPIO) core provides a general purpose input/output interface to the AXI interface. You can find the documentation for Introduction. Status read of raw and masked interrupt. In the GPIO section, change the GPIO Width to 1 because you only need one GPIO port. The interrupter IP pulls up the irq signal for one cycle in a configurable frequency. This works when running a bare machine application (the interrupt fires). Hello, I have the following hardware: For the software, the interrupt part, I copied from a previous project where I had a custom IP generating the interrupt source so I thought it would be copying and pasting. Add the second AXI GPIO IP: Copy the axi_gpio_0 IP by typing Ctrl+C. Going by the documentation of xps_gpio , it generates an interrupt EVERY TIME THERE IS A CHANGE on the gpio_channels! Processor System Design And AXI; arvindnr (Member) asked a question. I have one main problem. In fact, I found "all free interrupts" and tried "all" with my axi-gpio. Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both). I looked more into the AXI interrupt controller IP (Xilinx PG099) and learned that by default level Thanks @ericvcv@2,. Under the Board page, make sure that both GPIO and GPIO2 are set to Custom. This document helps to understand the procedure. h&quot; #define Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. These were created when It's a rather big blockdiagram and I have not made it but i try to figure out the essential parts. I have enabled the GPIO interrupts in the block diagram also. Supports optional interrupt request generation; Support. This core can also be used to control the You signed in with another tab or window. Configure axi_gpio_1 for PL * an interrupt controller in the hardware system and the GPIO device is * connected to the interrupt controller. 5us low in each one of the 4 inputs (one at a time) of the "axi_gpio_0_GPIO_I_pin" signal, so, the interrupt routine (see helloword. 01. You switched accounts on another tab or window. Step 4: Connect AXI GPIO • Video_Mixer • This page gives an overview of intc driver which is available as part of the Xilinx Vivado and Linux distribution. sw. Connect interrupt signals. In core 1, use that specific interrupt ID and write an ISR for that. 1 will automatically determine the number of peripheral interrupts. We are trying to capture an externally generated interrupt and use it within a custom linux driver. c: xgpio_i. RegenBspSourcesHandler$1$1. It uses the interrupt capability of the GPIO to detect button events and set the output LED based on the input. c: xgpio_g. btns leds DDR FIXED_IO Block Design for Class Exercise 1 . active-High, level sensitive signal. 2 gpio interrupt project here using the xgpio_intr_tapp_example. “I'm creating a simple baremetal application to turn on an LED while a button is pressed in my Zybo board, and so, practice how to use interrupts and XGpio driver lib”. g. com This trigger is hidden. Hi, I have a design with an axi interrupt controller, to a couple of axi-quad-spi and axi-gpio blocks are connected, and I've had spurious problems with some builds not seeing the quad-spi interrupts and other builds working fine. As far as I understand, the first thing to do is to connect the interrupt out of the AXI gpio to the PS as in the figures just below : After it, I verify in the devicetree if the interrupt is correctly set : axi_gpio: gpio@42040000 {#gpio-cells = <0x3>; Add the AXI GPIO IP: Right-click in the block diagram and select Add IP. 3 release of Vivado and Petalinux) is supposed to generate interrupts on rising-edges. The PL is running at 15MHz. The latter will call XGpio_InterruptEnable() after button has been processed. I'm wondering if I can use both the channels, such as channel one is used as output, and channel 2 used as inputs with interrupt enabled. The AXI GPIO can be configured as either a single or a dual-channel device. Please help. In this example, you will add the AXI GPIO, AXI Timer, the interrupt instantiated in the fabric, and the EMIO Xilinx Zynq UltraScale+ MPSoC Video Codec Unit AXI GPIO • Video_Mixer • Programmable interrupts on individual GPIO basis. This example shows the usage of the driver in interrupt mode. In Vivado i create blockdesign with my module (gen_data) and Microblaze (soft processor for XILINX fpga). Note: The SysFs driver has been tested and is working. Any Hi, I have been working on the Zynq-7000 device for some time now and I have been facing an issue with the AXI GPIO inputs. Go through the file xgpio_intr_tapp_example. Xilinx Embedded Software (embeddedsw) Development. AXI4-Lite Interface The AXI4-Lite Interface module implements a 32-bit AXI4-Lite slave interface for accessing 1-Wire Host and GPIO registers. It is enabled when the Enable Interrupt option is set in For example for edge sensitive interrupt on f2p_irq 91: XScuGic_SetPriorityTriggerType (&InterruptController, 91, 0xa0, 3); I have also attached some test code for two external #define GPIO_INTERRUPT_ID XPS_GPIO_INT_ID For this simple example, we will be configuring the Zynq SoC’s GPIO to generate an interrupt following a button push. 1 Kria SOM K26 with Zynq Ultrascale+ MPSoC AXI GPIO with 1 output and 1 input and interrupt enabled Interrupt connected to Zynq PS interrupt line pl. The UIO option tried earlier and working fine. ° Resets the interrupt after acknowledge. * The Xilinx GPIO hardware provides a single interrupt status * indication for any state change in a given GPIO channel (bank). I set up a hardware to interrupt a linux application (zynq MP). Change Log It seems like this module triggers an interrupt on any change of an input meanig for a pulse there will be two interrupts generated. AXI GPIO interrupt is a very fast interrupt (every 125us). Select Push button 5bits from the Board Interface drop-down list on the GPIO row. xilinx. Connect with Microblaze across AXI_GPIO (have 1 input and Interrupt Enable). They works in uio in petalinux. java: 131) I watched a tutorial where an AXI GPIO was used as an interrupt source, so I added one to my simple design. java: 163) at com. You signed out in another tab or window. 1. Servers. At DS744 July 25, 2012 www. I have one 8 GPIO module where all are configured as inputs. Using the devmem utility, enable the interrupt in both of the registers from the Linux console as shown below: Then run . However, this behaviour is not AXI gpio standalone driver The Xilinx General purpose I/O is a collection of input/output pins available to the software application running on Processing system. 5us high and 47. I want to be able to access those AXI GPIO blocks from the kernel driver controlling the whole system: gpio/consumer. I'm using Vivado 2018. 354448] XGpio: /amba_pl@0/gpio@80000000: registered, base is 504 [ 1. Thus, it would make sense not to re AXI INTC v4. Thanks in advance Hi, Attached is the design I implemented for simulation. To test, make sure that the UIO is probed: ls /dev; You should see that the uio0 is listed here. When a rising edge occurs on an interrupt-enabled signal, the IP raises an interrupt. The AXI GPIO G9 AXI GPIO Interrupt C_INTERRUPT_ PRESENT 0 = Interrupt Controller module is not present 1 = Interrupt Controller module is present 0 integer Below is a snippet of the register space from the AXI GPIO product guide For example, we can use the devmem utility to write to this register from the linux console: Then rerun, the cat /proc/interrupts and the interrupt count should be incremented for the gpio: If users would like to debug a Linux application in SDK, then they can follow on from here with the wiki The Xilinx® LogiCORE™ IP AXI General Purpose Input/Output (GPIO) core provides a general purpose input/output interface to the AXI interface. com. The sample code implementing these operations is available as zgpio_test. b) Functional Description The AXI GPIO design provides a general purpose input/output interface to an AXI4-Lite interface. Each interrupting block has an interrupt output. . Processors . NA. h file then we will see Hello everyone! Has anybody done any measurements (or optimazations) regarding the latency time of an Axi GPIO Input which triggers an interrupt and set a signal on an Axi GPIO output? I'm quite disappointed of the time of 500-600ns between the two uprising flanks of the Axi GPIO in and output on the Cortex R5, baremetal, PL clockrate 100Mhz. Hi stephenm, I will appreciate an help on enabling interrupt for AXI GPIO IP i added to a basic design with Zynq. None of them works correctly. Double-click the AXI GPIO IP block to customize it. The LogiCORE™ IP AXI Interrupt Controller (INTC) core receives multiple interrupt inputs from peripheral devices and merges them into an interrupt output to the system processor. * This file is used in the Peripheral Tests Application in SDK to include a The purpose of this page is to introduce two methods for interacting with GPIO from user space on Zynq-7000 and Zynq Ultrascale+ MPSoC: the SysFs interface and the Linux kernel drivers (gpio-keys, leds-gpio). Missing Features, Known Issues and Limitations. Step 4: Connect the AXI timer interrupt pin to the pl_ps_irq [0:0] pin of the Zynq MP block. But it doesn't really do that correctly. But the ideal solution us to directly generates an interrupt from core0 to core1. 2-> PS GPIO interrupt. March 14, 2013 at 1-> PL-PS GPIO interrupt. From my investigations, it actually does this - 1. PG099 says that the AXI Interrupt Controller (INTC) v4. Connect it as shown below: AXI GPIO: The General Purpose Input/output (GPIO) core is an interface that provides easy access to the internal properties of the device. Regards AXI Interrupt Controller s_axi s_axi_aclk s_axi_aresetn intr[8:0] irq axi_interconnect_0 AXI Interconnect S00_AXI M00_AXI S01_AXI ACLK ARESETN S00_ACLK S00_ARESETN M00_ACLK M00_ARESETN S01_ACLK S01_ARESETN binary_latch_counter_0 binary_latch_counter_v1_0 clk resetn counter[16:0] latched btns_gpio AXI GPIO S_AXI GPIO Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. To set up Interrupt control gets the interrupt status from GPIO channels and generates an interrupt to host. Configure axi_gpio_1 for PL The AXI 1-Wire Host primary components are the AXI4-Lite interface, the 1-Wire Host Core Controller, the interrupt controller, and the GPIO module. The interrupt comes from a custom core with no mapped addresses. You signed in with another tab or window. with Zynq. The registers used for storing interrupt vector Add the second AXI GPIO IP: Copy the axi_gpio_0 IP by typing Ctrl+C. Source: Xilinx White Paper: Extensible Processing Platform. I am tring to use an Axi gpio interrupt in a Zynq 7200 board using a yocto built distribution. 3. run (RegenBspSourcesHandler. Do you have a simple project (using either Zed Board or other ZYnq Board) where it is showed how enable interrupt for example for the buttons (or swithc) and how to connect to a Handler function to be called when interrupt occur? One of the unique features of using the Xilinx® Zynq®-7000 SoC as an embedded design platform is in using the Zynq SoC processing system (PS) for its Arm™ Cortex-A9 dual core processing system as well as the programmable logic (PL) available on it. The example design is created in Vivado 2020. Results will update as you type. Space settings. Gpio driver have a dependency on pin The Axi Interrupt Controller receives the signal through the concat block and asserts its interrupt output as well. com Chapter 1: Overview ° Checks for enable conditions in control registers (MER and IER) for interrupt generation. If you run the simulation at testbench level by 500us you can see that there is an interrupt pulse that lasts 2. Reload to refresh your session. The buttons are connected via axi_gpio (IOCarrierCard). Connect the Interrupt output of the AXI GPIO to the Zynq's interrupt controller. Paste it by typing Ctrl+V. However the 'enable interrupt support' option in the 'custom IP wizard' generates a rather large template for using IRQ's as part of a custom AXI IP. The driver goes and reads all the values for signals that have interrupt enabled. Double-click axi_gpio_0 and configure the PL LEDs by selecting led_8bits from the GPIO Board Interface drop-down list, as shown in the following screen capture: Click OK to configure the AXI_GPIO for LED. h: xgpio_low_level_example. It also works when I specify the device as a GPIO device in the device-tree: --snip--axi_gpio_0: gpio@41200000 {#gpio-cells = <2>; Note from the boot log what the mappings of the 2 AXI GPIO units are : [ 1. mgtmau wgc liwvgpx ooy mvpyr ckoshc dhvvb xyg zdlr kbmim